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Re: More measurements

To: Jes Sorensen <jes@xxxxxxxxxxxxx>
Subject: Re: More measurements
From: Andrew Morton <andrewm@xxxxxxxxxx>
Date: Wed, 31 Jan 2001 11:37:28 +1100
Cc: netdev@xxxxxxxxxxx
References: <3A75785A.42B9E7CE@xxxxxxxxxx>, Andrew Morton's message of "Tue, 30 Jan 2001 01:04:10 +1100" <d3g0i04vb5.fsf@xxxxxxxxxxxxxxxxx>
Sender: owner-netdev@xxxxxxxxxxx
Jes Sorensen wrote:
> >>>>> "Andrew" == Andrew Morton <andrewm@xxxxxxxxxx> writes:
> Andrew> - eepro100 generates more interrupts doing TCP Tx, but not TCP
> Andrew> Rx.  I assume it doesn't do Tx mitigation?
> Andrew> - Changing eepro100 to use IO operations instead of MMIO slows
> Andrew> down this dual 500MHz machine by less than one percent at 100
> Andrew> mbps.  At 12,000 interrupts per second. Why all the fuss about
> Andrew> MMIO?
> Ingo or Don Becker (sorry don't remember if it was Ingo or Don) did
> some tests showing that the write speed to IO ports was about 10 times
> the slower and read about 5 times slower. There is also the issues of
> stalling the bus. This may not all show up in actual transmission
> speeds etc.


Question: when the CPU reads from a PCI location, are the
CPU <-> PCI bridge buses blocked for the duration of the
read, or does the PCI bridge reconnect?

I'm guessing that the major benefit of MMIO is posted
writes: getting the CPU off the memory bus quickly.

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